Photodetector-arrays, such as those which are included or which constitute image-sensors and FPAs, generally include an array including a plurality of light/photosensitive detection elements/regions (referred to as photodetectors) which generate photocurrent in response to light impinging thereon, and a corresponding readout integrated circuit (ROIC) including an array of readout integrated circuit pixels (RICPs) capable of receiving and/or storing and/or processing the signals/data indicative of the photocurrents for the respective photodetectors to allow further readout of these signals/data by an external processing utility such as an image processing unit (IPU) and/or a graphical processing unit (GPU). In the following description the term pixel designates a photodetector (e.g. light-sensitive-detection-region/element) and its respective RICP electrically connected together, and the term photodetector-array designates an array of such pixels. Photodetector-arrays are used in a variety of fields to capture and record spatial, spectral and/or temporal light signatures (hereinafter generally referred to as images) coming from objects/scenes. The images and/or light signatures are captured on a plurality of detection elements, where different photodetectors of the image sensors capture different spatial and/or spectral portions of the object/scene that needs to be recorded.
Conventional photodetector-arrays (configured and/or fabricated using known in the art techniques), generally typically include a plurality of dysfunctioning pixels (i.e. defective/dead pixels), from which a proper electric signal indicative of the photocurrent/intensity-of-the-light-falling-thereon, cannot be extracted. For some applications, it is possible to make compromises and use less than perfect photodetector-arrays that may include a few or more defective/dead pixels. For other applications, strict, post fabrication quality inspections are conducted during/after the manufacturing procedure of the photodetector-arrays to identify and dispose of faulty photodetector-arrays in which the number and/or density of defective pixels exceeds a certain tolerable value. This leads to substantial increase of production costs and waste, especially in cases where the allowable/tolerable number/density of defective pixels is small, or in cases where existence of defective pixels is not allowed.
Accordingly, there are various known in the art techniques which are aimed at dealing with the existence of defective pixels. For instance U.S. Pat. No. 7,786,438 discloses a sensor assembly that replaces a single focal plane array detector with two focal plane array detectors. The two focal plane array detectors are orientated with respect to each other such that a power splitter divides an incoming light source equally between each detector. The two detectors are selected such that the locations of poorly-operating pixels in each detector do not overlay. The output signals of each detector are then electronically or analytically combined to yield 100 percent operability.
Other techniques are aimed at reducing defect density in the semiconductor devices. For example U.S. patent application No. 2004/121507 discloses a method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density. The method includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.
Also, an attempt to reduce dysfunctional pixels is described in “Low Temperature Fluxless Technology for Ultra-fine Pitch and Large Devices Flip-chip Bonding” by C. Davoine, M. Fendler, F. Marion, C. Louis, G. Destefanis, R. Fortunier, Electronics Packaging Technology Conference, 2005, According to this technique, room temperature interconnection technology is used to obtain flip-chip bonding between the detector die and the ROIC die at room temperature, in order to reduce residual strain and warpage of the assembly due to coefficients of thermal expansion (CTE) mismatch between the dies.
General Description
The present invention relates to image sensors and FPAs which are configured as hetero sensor chip assemblies (HSCA) including a detector die, being a first semiconductor structure fabricated with a first semiconductor technology/material and a readout integrated circuit (ROIC) die, being a second semiconductor structure fabricated with a second semiconductor technology/material different than the first semiconductor technology.
It should be noted that the phrase semiconductor technology is used herein to refer to semiconductor structures whose layers are made using particular types of semiconductor materials/compositions and/or super-lattices, and to methods of fabrication of such structures. In this sense the phrase different semiconductor technologies refers to semiconductor structures/methods of particular types of semiconductor materials/compositions and/or super-lattices. In this regard, in the framework of the present invention, a difference in the CTEs of different semiconductor technologies in the HSCA is particularly significant.
Typically, the HSCA defines a two dimensional array of pixels, each comprising a light sensitive region/element (hereinafter referred to as a photodetector) in the first semiconductor structure of the detector die and a corresponding ROIC in the second semiconductor structure of the ROIC die. To this end, the first semiconductor structure defines a matrix/array of light sensitive regions (photodetectors), and the second semiconductor structure defines a complementary matrix/array of readout integrated circuit pixels (RICPs). The first and second semiconductor structures are coupled with electrical interconnects (bumps) between the respective photodetectors and RICPs, for example by flip-chip bonding/configuration which can be followed by a so called reflow process. More specifically, a flip chip bonding process typically includes the following steps:                1. Aligning the ROIC and photodetector pixels at a certain temperature. Alignment temperature is lower than the melting/freezing point of the metal bumps.        2. Applying force in order to bring in contact opposite bumps.        3. In the reflow process the already connected HSCA is heated above the melting/freezing temperature of the metal the bumps are made-of, and cooling down to form a better connected bond.        
As a result the array of photodetectors is electrically connected to the array of RICPs, such that the photocurrent from the photodetectors is received and stored/processed by respective RICPs.
In many cases, in particular where image-sensors/FPAs configured for sensing light in spectral bands other than the visual band (e.g. IR sensors), are concerned the first semiconductor structure, in which the light sensitive photodetectors are defined, and the second semiconductor structure (ROIC), in which the RICPs are defined, are made of different semiconductor technologies/materials. For instance, the semiconductor structure of the ROIC may be made using Silicon (Si) semiconductor technology/material, while the semiconductor structures defining the light sensitive photodetectors in some IR ranges may be configured/made using type III-V semiconductor technology/material-compositions and/or using type II-VI semiconductor technology/material-compositions, such as Mercury Cadmium Telluride (MCT), or may be configured and operable as HSCA sensors for sensing radiation in other spectral ranges, such as X-Ray and/or ultraviolet (UV) range.
Modern image sensors and FPAs include millions of pixels. For the pixels to work properly, there is a need for good alignment and good electrical contact between the correlative photodetectors of the detector and the readout integrated circuits ROIC.
The inventors of the present invention have noted that in many cases, mismatch between the CTEs of the first and second semiconductor structures (the photodetectors and ROICs semiconductor structures) results in dead/dysfunctioning pixels in the photodetector-array. This is because during the process of electrical bonding between the photodetector and ROIC pixels (RICPs), which is carried out at relatively high temperatures (e.g. in the order of 150° C. to 250° C.), there exists misalignment between the photodetectors and ROICs (due to difference in their CTEs), which in turn results in not all photodetectors being properly electrically connected to their respective RICPs.
To solve this, the present invention, in a first aspect thereof, provides a novel method for fabricating a photodetector-array. The method includes:                providing a first semiconductor structure made according to a first semiconductor technology having a first coefficient of thermal expansion (CTE) and including an active region including a plurality of light sensitive regions associated with respective electric contacts. The light sensitive regions serve as active photodetectors of the photodetector-array.        providing a second semiconductor structure made according to a second semiconductor technology having a second CTE. The second semiconductor structure includes a plurality of active readout integrated circuits pixels (RICPs) configured and operable for carrying out readout operations from the active photodetectors. To this end the RICPs have respective electric contacts for connecting to the electric contacts of the active photodetectors;        aligning the first and second semiconductor structures at first temperature conditions such that the array of active photodetectors is substantially parallel and aligned with the array of active readout circuits; and        carrying out electrical coupling between the electric contacts of the active photodetectors and the respective electric contacts of the RICPs.        
The first and second CTE of the first and second semiconductor structures may not match. Therefore, according to the present invention, the pitch distances of the electric contacts of the active photodetectors in the first semiconductor structure and pitch distances of the respective electric contacts of the active RICPs in the second semiconductor structure are configured in accordance with a difference between the first and second CTEs such that at high temperatures (at which the electrical coupling is performed) the electric contacts of the active photodetectors overlap with respective ones of the readout electric contacts of the active readout circuits.
In some embodiments of the present invention, the pitch distances of the electric contacts and the pitch distances of the respective electric contacts are selected such that at these high temperatures, most (e.g. 99.5% or more preferably more than 99.9%), or all, of the active photodetectors are respectively electrically coupled exclusively to their respective RICPs.
In some embodiments of the present invention the electrical coupling further comprises cooldown of the first and second semiconductor structures after the electrical coupling is performed while maintaining the exclusive electrical coupling between all the active photodetectors and respective RICPs thereof.
In some embodiments of the present invention the electrical coupling is performed by soldering electrical connection bumps between electrical contacts of the first and second semiconductor structures. In some embodiments the soldering includes heating the first and second semiconductor structures to the high temperature which is above a melting temperature of the electrical connection bumps. In some embodiments the electrical coupling includes a reflow process at which the first and second semiconductor structures are heated to high temperature being in the order of 150° C. to 250° C. It is noted that in some embodiments improved bonding is achieved by bonding the first and second semiconductor structures in “non-reflow” process. In such “non-reflow” process the first and second semiconductor structures are pressed together to contact their opposing electrical connection bumps, and are heated to temperatures that are below the melting temperature of the electrical connection bumps.
In some embodiments of the present invention the electrical coupling further includes cooling of first and second semiconductor structures to freezing temperature of the electrical connection bumps. The pitches of the electric contacts of the active photodetectors and pitches of the respective electric contacts of the RICPs are arranged such that, at the freezing temperature, the electric contacts of the active photodetectors overlap with corresponding respective electric contacts of the RICPs.
In some embodiments of the present invention the pitch distances of the electric contacts of the active photodetectors and the pitch distances of the respective electric contacts of the RICPs substantially do not match at a temperature at which the aligning is performed.
In some embodiments of the present invention the array of active photodetectors includes more than 1280×1024 active photodetectors with a pitch of 10 microns and preferably includes about 1920×1536 active photodetectors with a pitch of 10 microns.
In some embodiments of the present invention the first semiconductor structure includes two or more alignment features and the second semiconductor structure includes two or more complementary alignment features. The alignment features and the complementary alignment features are arranged such that, at certain alignment temperatures, at which the alignment is performed (which is substantially lower than the high temperature of the reflow), the displacements between pairs of the alignment features match displacements between respective pairs of the complementary alignment features. This thereby facilitates achieving accurate alignment between the first and second semiconductor structures during the aligning (for example by locating the first and second semiconductor structures such that the alignment features and the second alignment features are co-aligned). In some embodiments the alignment temperature is within the range from about an ambient temperature and not exceeding freezing temperature of electrical connection bumps used to couple the first and second semiconductor structures (e.g. in the range between 20-120° C.).
In some embodiments of the present invention the alignment features include one or more alignment features arranged at a peripheral region surrounding the active photodetectors, and the complementary alignment features include one or more features similarly arranged at a peripheral region outside a region of the active RICPs. In some embodiments the alignment features and the complementary alignment features include respective alignment marks made in the first and second semiconductor structures. In some embodiments the alignment features include a group of non-active photodetectors in the first semi-conductor structure. Also, in some embodiments, during electrical coupling, at least some non-active photodetectors of the group of non-active photodetectors are electrically coupled to a Common contact of the second semiconductor structure. In some embodiments the complementary alignment features include a group of non-active RICPs in the second semiconductor structure. To this end, in some embodiments the non-active RICPs are associated with ground or common contacts of the second semiconductor structure.
In some embodiments of the present invention the method of includes at least one of the following operations:                providing at least one of the first and second semiconductor structures in the form of a thin film structure;        mechanically attaching at least one semiconductor structure of the first and second semiconductor structures to a stabilizing structure made of a material composition having different CTE than the at least one semiconductor structure; and        placing bond materials between the first and second semiconductor structures;        
thereby providing mechanical stabilization of the photodetector-array against stresses and/or strains formed between the first and second semiconductor structures at temperatures lower than the high temperature.
In some embodiments of the present invention the first semi-conductor structure comprises one of the following semiconductor materials: group III-V, group II-VI, group IV-VI, and group IV; and the second semi-conductor structure comprises silicon (Si) semiconductor material.
In another aspect, the present invention provides a novel photodetector-array that includes:                a first semiconductor structure made according to a first semiconductor technology having a first coefficient of thermal expansion (CTE) and comprising an active region including a plurality of active photodetectors each including a light sensitive region of the first semiconductor structure and respective electric contacts;        a second semiconductor structure made according to a second semiconductor technology having a second CTE different than the first CTE and including a plurality of active readout integrated circuit pixels (RICPs) configured and operable for carrying out readout operations from the active photodetectors. The RICPs have respective electric contacts for connecting to the electric contacts of the active photodetectors.        
A photodetector-array, which is configured according to embodiments of the present invention and/or fabricated/assembled by the method of the present invention, can/might be identified and/or distinguished from photodetector-arrays fabricated/configured according to other techniques, in that a photodetector-array of the invention may include an active region, which includes a continuous array of mostly fully functional (non-defective) active pixels (with more than 99.5% functional pixels). In some embodiments about 99.9% of the active pixels are properly electrically connected to their respective RICPs. In other words, the continuous array of functional pixels is continuous in the sense that not more than 0.5% of the pixels in the active region are defective pixels and preferably not more than 0.1% of defective pixels (namely having mal connection to their respective RICPs or other defect) exists among (located between) the active pixels in the active region. In this regard it is noted that according to some embodiments of the present invention, the lateral size/dimension of the active region (of the array of active pixels) extends at least 1920 pixels along at least one lateral direction/axis. To this end, it should be noted that lateral extent/size of some conventional HSCA photo-detectors arrays, such as those comprising InSb materials do not exceed 1280 pixels alone any lateral direction, without having many (>2%) defective pixels not properly electrically connected to their respective RICPs.
To this end, much smaller photodetector-arrays (e.g. with a fewer number of elements (pixels), are obtained when using conventional techniques for coupling detector dies to ROIC dies by reflow process, as compared to the achievable size/number of elements in the technique of the present invention. For example, conventional techniques allow fabrication of HSCA with InSb photodetection die and Si ROICs die with an array of about 1280*1024 elements/pixels arranged with 15 micron pitch. Above this size/number of elements, using a reflow process according to conventional techniques results in too many defective pixels (e.g. more than about 2%). Indeed, achieving a higher number/density of pixels in conventional techniques is possible by the use of cold coupling techniques (not reflow techniques, such as room temperature interconnection technologies). However, the latter has major disadvantages associated with low quality of the coupling/electric contacts between the dies and/or non-uniform coupling. In comparison, the technique of the present invention enables fabrication of HSCA including InSb photodetection and Si ROIC dies, with more than twice the number of elements and with similar dimensions (e.g. the present technique allows fabricating an array of similar 1920*1536 elements from these materials with a pitch of only 10 microns namely with about twice the density obtained in conventional reflow based techniques), while using reflow to couple the photodetection and ROIC dies. Experiments for fabrications of such an HSCA (having InSb photodetection and Si ROIC dies and defining 1920*1536 elements arranged with pitch of 10 microns) by using the conventional reflow techniques have resulted in too many defective pixels, more than about 2% of the pixels. In a similar manner, the technique of the present invention enables fabrication of HSCA including a GaSb based photodetection die and a Si ROIC die with an array of 1920*1536 with 10 micron pitch. In comparison, conventional techniques, which are based on the reflow process, obtain arrays of 640*512 elements/pixels with 15 micron pitch, when using these materials. To this end the present invention has a significant advantage over conventional techniques, as it allows to fabricate HSCA with pixel arrays having a significantly higher number of elements and/or significantly higher density of the elements, while using hot bonding (e.g. bonding based on reflow process) reflow between the photodetection and ROIC dies.
Alternatively or additionally, a photodetector-array, which is configured/fabricated according to an embodiments of the present invention, can/might be identified and/or distinguished from conventional photodetector-arrays in that it includes: (a) an array of active pixels which are associated/arranged with a first pitch distance between them; and (b) a plurality of alignment features/markers (e.g. which are used for aligning between the first (photodetectors) and second (ROIC) semiconductor structure), associated with a second pitch distance between them different than the first pitch distance of the active pixels.
Alternatively or additionally, a photodetector-array, which is configured/fabricated according to an embodiment of the present invention, can/might be identified and/or distinguished from conventional photodetector-arrays, in that the plurality of alignment features markers are arranged in the periphery of the array of active pixels (e.g. at a region outside/surrounding the continuous array of active pixels).
In some embodiments of the photodetector-array of the invention, the arrangement and pitch distances between the electric contacts of the active photodetectors in the active region match an arrangement and pitch distances between the electric contacts of the RICPs. Accordingly, the electric contacts of all or most (e.g. 99.9% or more) of the active photodetectors are aligned with, and are properly electrically connected to electric contacts of respective RICPs. Also in some embodiments the electric contacts of the active photodetectors are electrically connected exclusively to the electric contacts of respective RICPs.
In some embodiments the active photodetectors are arranged in the active region in a regular two dimensional array layout defining rows and columns of the active photodetectors, with even horizontal and vertical spacing between respectively adjacent rows and adjacent columns. The active RICPs are arranged in a two dimensional array layout similar spacing between respectively adjacent rows and adjacent columns of the two dimensional array as in the regular array layout of the active photodetectors. The first and second semiconductor structures are bonded to each other in flip chip bonding configuration and the electrical contacts of the active photodetectors are soldered to the electrical contacts of the RICPs with soldering bumps.
In some embodiments of the present invention the first semiconductor structure includes two or more alignment features located outside the active region, and the second semiconductor structure includes two or more complementary alignment features with arrangement matching to the two or more alignment features. The first semiconductor and second semiconductor structures are assembled and bonded together, such that the pitch distances between at least some of the two or more alignment features are different than pitch distances between the corresponding ones of the two or more complementary alignment features, at the final assembled device. Namely, the pitches and arrangement of the alignment features and their complementary alignment features match during an intermediate alignment stage/temperature of the assembly of the device (e.g. but don't match at the reflow stage at which the dies are coupled/bonded together).
As indicated above in some embodiments of the photodetector-array of the invention, the alignment features and/or the complementary alignment features may include respective alignment marks and/or complementary alignment marks which are made in the first and/or second semiconductor structures. Alternatively or additionally, the alignment features may include non-active photodetectors in the first semi-conductor structure located outside the active region. In some cases the alignment features are associated with overlapping contact pads in the first and second semiconductor structures which provide Common contact between the first and second semiconductor structures.
According to some embodiments, the photodetector-array of the present invention includes at least one of the following features which mechanically stabilizes the photodetector-array against stresses and/or strains formed due to differences in the CTEs of the first and second semiconductor structures:                at least one of the first and second semiconductor structures in the form of a thin film structure;        a stabilizing structure attached to at least one of the semiconductor structures and having different CTE than the CTE of the one semiconductor structure; and        bonding materials placed between the first and second semiconductor structures.        
In some embodiments the photodetector-array includes more than 1280×1024 active photodetectors arranged with a pitch of 10 microns, and more preferably includes about 1920×1536 active photodetectors with a pitch of 10 microns.